The present invention relates to fast programmable Electrically Erasable Programmable Read-Only Memory devices and method for operating such devices.
Nowadays, most Flash memories use Channel Hot Electron Injection (xe2x80x9cCHEIxe2x80x9d) at the drain side of the memory cell, or Fowler-Nordheim Tunnelling (xe2x80x9cFNTxe2x80x9d) for programming. The Channel Hot Electron Injection mechanism provides a relatively high programming speed (xcx9c10 xcexcs) at the expense of a high power consumption (xcx9c400 xcexcA/bit) which limits the number of cells that can be programmed simultaneously (so-called page-mode programming) to a maximum of 8 bytes (Y. Miyawaki et al., IEEE J. Solid-State Circuits, vol.27, p.583, 1992). Furthermore, in order to allow a further scaling of the transistor dimensions towards 0.18 xcexcm and below, supply voltage scaling from 3.3V towards 1.8V also becomes mandatory. This supply voltage scaling is known to degrade the Channel Hot Electron Injection efficiency and, hence, the corresponding programming speed considerably. These memories already use a bitline charge pump to provide a 4-5V drain voltage to the cell during programming and erasing. The problem with this solution is two-fold: (1) since the internally generated programming voltages are not scaled down with respect to the technology generation, it becomes practically impossible to further scale the cell itself, in terms of both vertical (dielectric thicknesses) and lateral (gate length) dimensions; (2) due to the high power needed to trigger the Channel Hot Electron Injection, it becomes harder and harder to supply these voltages on-chip from a high voltage generator or charge pumping circuit. Also, the relative area of the charge pumps and the corresponding high-voltage switching circuitry increases with respect to the useful area of the memory chip.
On the other hand, tunnelling provides slower programming times (xcx9c100 xcexcs) and a low power consumption which allows larger pages (xcx9c4 kbit) in order to reduce the effective programming time to 1 xcexcs/byte (T. Tanaka et al., IEEE J. Solid-State Circuits, vol.29, p.1366, 1994). However, a further improvement is limited by tunnel-oxide scaling limits and by the very high voltages (xcx9c15V) needed on chip for Fowler-Nordheim Tunnelling, both compromising device reliability and process scalability.
The recent success of Source-Side Injection (xe2x80x9cSSIxe2x80x9d) as a viable alternative over Fowler-Nordheim Tunnelling and Channel Hot Electron Injection for Flash programming is mainly due to its unique combination of moderate-to-low power consumption with very high programming speed at moderate voltages. A typical example of such a device relying on Source-Side Injection for programming is the High Injection Metal-Oxide-Semiconductor or HIMOS(copyright) memory cell (J. Van Houdt et al., 11th IEEE Nonvolatile Semiconductor Memory Workshop, February 1991; J. Van Houdt et al., IEEE Trans. Electron Devices, vol.ED-40, p.2255, 1993). As also described in the U.S. Pat. Nos. 5,583,810 and 5,583,811, a speed-optimized implementation of the HIMOS(copyright) cell in a 0.7-xcexcm CMOS technology exhibits a 400 nanoseconds programming time while consuming only a moderate current (xcx9c35 xcexcA/cell) from a 5V supply. This result is obtained when biasing the device at the maximum gate current, i.e. at a control-gate voltage (Vcg) of 1.5V. The corresponding cell area is in the order of 15 xcexcm2 for a 0.7-xcexcm embedded Flash memory technology when implemented in a contactless virtual ground array as described in pending application Ser. No. 08/426,685, incorporated herein by reference. In terms of the feature size F (i.e. the smallest dimension on chip for a given technology), this corresponds to xcx9c30F2 for a 0.7-xcexcm technology. This is fairly large as compared to the high density Flash memory concepts which are all in the xcx9c10F2 range.
However, due to the growing demand for higher densities, also in embedded memory applications like e.g. smart-cards and embedded microcontrollers, a continuous increase in array density and the scaling of the supply voltage become mandatory. This evolution calls for more aggressive cell-area scaling and for low-voltage and low-power operation. In the co-pending application Ser. No. 08/694,812, incorporated herein by reference, a programming scheme is described which reduces the power consumption during the write operation considerably. Also, the used write voltages are expected to scale with the supply voltage Vsupply since the Source-Side Injection mechanism only requires the floating-gate channel to stay in the linear regime for fast programming (see e.g. J. Van Houdt et al., IEEE Trans. Electron Devices, vol. ED-40, p.2255, 1993). Therefore, the necessary Program-Gate voltage Vpg for fast programming is given by:
Vpg≈(Vsupply+Vth)/pxe2x80x83xe2x80x83(1)
wherein Vth is the intrinsic threshold voltage of the floating gate transistor (xcx9c0.5V) and p is the coupling ratio from Program Gate to Floating Gate (typically xcx9c50%). According to Eq.(1), Vpg is thus expected to scale twice as fast as the supply voltage in a first order calculation. It can be concluded that the high programming voltage is scaling very well with the supply voltage and offers enough margin in order for the high voltage circuitry to follow the minimum design rule. These and other features described in the related patents and patent applications indicate the high scalability of the HIMOS(copyright) concept in comparison with the traditional cells that use drain multiplication or tunnelling.
However, there are some drawbacks in the HIMOS(copyright) cell concept. First, there is a drawback of the additional program gate, which increases the cell area considerably in the case of a double polysilicon technology. Furthermore, since both a control gate and a program gate are formed in the same polysilicon layer, the process requires special polysilicon etching recipes in order to remove the polysilicon stringers between the control gate and the program gate. Another drawback is related to the decoder design. Since the cell is erased with negative gate voltages on the control gate and program gate, as described in the pending application xe2x80x9cMethod of erasing a Flash EEPROM memory cell optimized for low power consumptionxe2x80x9d, U.S. Pat. No. 5,969,991 issued Oct. 19, 1999, a pMOS transfer gate is required in the row decoder. During read-out (a program gate voltage is set to zero) and during the write/read deselect operations (a control gate voltage is set to zero), a negative voltage is required to switch the ground potential onto the gates of the array. This in turn requires a small charge pump in the row decoder, which has a small but negative impact on the access time and power consumption. Further, there is a reliability problem associated with the program gate""s disturb phenomenon. After a cell has been programmed, the high program gate""s programming voltage (typically 9V in a 0.35 xcexcm technology) can cause discharging of this cell while programming other cells on the same row. Alternatively, erased cells can be slowly programmed because of tunnelling through the tunnel oxide. Further, another problem is due to the appearance of Stress-Induced Leakage Current (xe2x80x9cSILCxe2x80x9d). When the cell has been written and erased for a large number of times, the tunnel oxide quality is deteriorated in such a way that the application of a small read-out voltage at the drain can cause slow discharging of programmed cells. Even though this is a very small leakage current, it has to be controlled for the entire lifetime of the device that is typically 10 years.
There have been many attempts to obtain a smaller cell using 3 polysilicon layers, as described in a co-pending PCT patent application Ser. No. PCT/BE98/00134, WO 9913513, filed Sep. 9, 1998. Other references to such devices are: (1) U.S. Pat. No. 5,284,784, issued Feb. 8, 1994, to Martin H. Manley; (2) U.S. Pat. No. 5,091,882, issued Feb. 25, 1992, to K. Naruke; (3) U.S. Pat. No. 4,794,565, issued Dec. 27, 1988, to A. T. Wu et al. (4) U.S. Pat. No. 5,235,544, issued Aug. 10, 1993, to J. Caywood; (5) U.S. Pat. No. 5,338,952, issued Aug. 16, 1994, to Y. Yamauchi; (6) U.S. Pat. No. 5,280,446, issued Jan. 18, 1994, to Y. Y. Ma et al.; and (7) U.S. Pat. No. 5,394,360, issued Feb. 28, 1995, to T. Fukumoto. These references all suffer from a number of significant disadvantages that are discussed now in more detail.
The first four referenced patents (Manley, Naruke, Wu and Caywood) all describe so-called xe2x80x9csidewall gatexe2x80x9d devices (FIG. 1). In each of these devices, the floating gate is formed in the first polysilicon layer, while the select gate is formed by a polysilicon sidewall spacer. This spacer can be formed in the second polysilicon layer (Manley, FIG. 1a) or in the third one (Wu, Naruke, Caywood, FIG. 1). There are main disadvantages associated with these sidewall-gate devices. First of all, the sidewall select gate is formed by depositing a polysilicon layer on the chip which is then removed selectively by using anisotropic (dry) etching techniques. However, it is very difficult to control this selective etching operation. For example, the width of the spacer remaining after etching determines the effective channel length during programming and this parameter should be tightly controlled. Therefore, this technique is not to be considered as a standard process step for CMOS. Also, after this anisotropic etch, the remaining sidewall is not only present on the source side of the device, but it will be a ring around the first and eventually also the second polysilicon gate(s). To correct for this problem, an additional photo step is required. Further, since the select gate controls a short portion of the channel, it needs to switch off the transistor channel in some cases, e.g. when reading/writing a particular cell the select gates of the (erased) cells sharing the same bitline have to be able to reduce their channel current to zero in order to prevent leakage currents and/or unwanted programming in the array. Usually, the thickness of the polysilicon, which determines the width of the spacer, is smaller than the minimum feature size that compromises the hard-off situation which in turn is highly desired in a memory array.
Further, the efficiency of the Source Side Injection mechanism is closely linked to the thickness of the oxide spacing in between the select and the floating gate (see e.g. J. Van Houdt et al., IEEE Transactions on Electron Devices, vol.39, no.5, May 1992). By putting the sidewall right next to the control gate (Wu, Naruke, Caywood), the oxide spacing has to remain fairly thick since it also has to isolate the high control gate voltage during programming from this sidewall gate. Therefore, the injection efficiency is compromized by isolation requirements. Also, since the part of the transistor channel which is controlled by the sidewall gate is much shorter than the part controlled by the floating gate, a larger portion of the external drain voltage will be lost for the channel hot-electron generation at the injection point. However, the main problem with these devices is the difficulty for contacting the cells in a large array of memory cells.
The sidewall gate is also used for wiring, and this has a considerable negative impact on the parasitic resistance in a large memory array, as explained in U.S. Pat. No. 5,394,360, issued Feb. 28th, 1995, to T. Fukumoto (col.1, lines 37-41). The 5th reference (U.S. Pat. No. 5,338,952, issued Aug. 16th, 1994, to Y. Yamauchi) removes some of the problems mentioned above by forming the floating gate as a polysilicon sidewall spacer (FIG. 1c). However, some drawbacks of the sidewall-gate device are still present in this memory cell. First of all, the sidewall select gate is still formed by depositing a polysilicon layer on the chip that is then removed selectively by using anisotropic (dry) etching techniques. In this case, the width of the spacer remaining after etching determines the effective channel length during the read-out process, and this parameter should be tightly controlled. Further, if electrons are stored on the floating sidewall gate, the portion of the channel controlled by this sidewall has to be switched off efficiently, which is not evident. As already mentioned above, the thickness of the polysilicon that determines the width of the spacer is usually smaller than the minimum feature size, which compromises the hard-off situation that is highly desired in a memory array. Eventually, the cell may exhibit a soft-on and a hard-on state instead of hard-off/hard-on states as required for fast access. Furthermore, since erasing is now to be achieved from the sidewall towards a sufficiently underdiffused drain junction, the effective channel controlled by the spacer is even smaller. This makes the leakage problem during read-out even more critical.
As in the previous cases, after the anisotropic etch, the remaining sidewall is not only present on the drain side of the device, but it will be a ring around the select gate. To correct for this, an additional photo step is required. Further, since the floating gate is a sidewall spacer, the coupling ratio between the control gate (3rd polysilicon) and this floating gate will be rather small. Indeed, referring to FIG. 1 in the Yamauchi application, it is clear that the couplings from the floating sidewall gate towards the control gate, substrate/drain and select gate are on the same order of magnitude. This implies that the high programming voltage is still 12V in a 0.5 xcexcm CMOS technology (see the corresponding conference paper xe2x80x9cA 5V-only virtual ground Flash cell with an auxiliary gate for high density and high speed applicationsxe2x80x9d, by Y. Yamauchi et al., IEDM Tech. Dig., p.319, 1991). Consequently, the voltage difference between the control gate and the select (or auxiliary) gate exceeds 10V during programming which compromises the scaling of the 2nd interpoly layer (layer 12 in FIG. 1 of the discussed application). Thus, this dielectric layer will have to remain relatively thick (200 xc3x85) according to the application (col.4, line 46). This will further decrease the coupling ratio between the control gate and the floating gate, since the oxide between the sidewall and the select gate has to scale because of its impact on the source-side injection efficiency (see above).
The only solution is to increase the coupling ratio by adding coupling area (so-called wings) between the control gate and the floating gate. However, this solution compromises the major advantage of this cell, which is its high integration density. Additionally, the erase voltage is still very high (xe2x88x9211V according to the application), which makes the concept unsuited for embedded memory applications where these high negative voltages would introduce too high an additional processing cost. This high erase voltage is again a consequence of the fairly low coupling ratio towards the sidewall gate.
Ma et al. (referenced patent 6) disclose an alternative memory cell with 3 polysilicon layers, which also uses the source-side injection mechanism (FIG. 1d). The major difference with the previously discussed prior art is the absence of a sidewall gate. Instead, first and second poly are etched in a stacked way and the select gate is added on top by a 3rd polysilicon layer. Some major disadvantages are given hereafter. First of all, it is well-known that such a processing scheme introduces considerable complexity which makes it impossible to use in an embedded memory application. On the other hand, the used erase voltage is still xe2x88x9212V provided that the bitline is biased at 5V. In future generations (when the supply voltage and hence also the bitline voltage go down), aggressive tunnel oxide scaling will be required in order not to have an increase of this negative voltage. Further, the oxide spacing between the select gate and the control gate has to be kept quite thick because this oxide also serves to isolate the high programming voltage from the select gate in order not to have a soft-erase effect or even oxide breakdown during programming. This restriction compromises scaling in general and, more in particularly, decreases the injection efficiency which is directly linked to the thickness of this spacing as explained extensively by J. Van Houdt et al. in IEEE Transactions on Electron Devices, vol.39, no.5, May 1992. U.S. Pat. No. 5,394,360, issued Feb. 28th, 1995, to T. Fukumoto, describes several embodiments of source-side injection cells.
The embodiment disclosed in FIG. 2 of the above-mentioned patent suffers from the same disadvantages as the device described by Ma et al. (see above). The second embodiment (FIG. 4 in that patent and FIG. 2 in the present application) still suffers from problems. For example, the dielectric determining the injection efficiency that is used for the spacing between select gate and control gate also has to provide sufficient isolation between the high programming voltage (2nd polysilicon) and the (low) select gate voltage during programming (3rd polysilicon). When examining the numbers from this patent, the control gate will be pulsed to 14-15V and the select gate is biased at 1.5V during programming (col.2, lines 59-64). This implies that the second interpoly dielectric is subject to a stress of 12.5-13.5V. Obviously, this layer can not be made very thin and, hence, the injection efficiency will be compromised since the same layer is also serving as the spacing oxide between select gate and floating gate (see FIG. 2).
A second problem with the Fukumoto cell is the following: the second polysilicon (control) gate should cover most of the floating gate in order to increase the coupling ratio and hence reduce the programming voltage. On the other hand, this overlap is limited due to design rules since the xe2x80x9coffset regionxe2x80x9d (col.1, line 59) has to be covered uniquely by the third polysilicon gate for having a functional cell. In practice, this layout rule will be about xc2xd of the feature size due to misalignment considerations (see FIG. 2). Since the floating gate has to be scaled as much as possible to minimize capacitive coupling ratios towards all terminals other than the control gate, its length will be xcx9cF in an efficient cell design. This implies that only 50% of the floating gate area will actually contribute to the coupling ratio. The statement (col.3, lines 34-37) that xe2x80x9cthe second gate electrode is provided so as not to enter (overlap) the offset region and to be directly capacitively-coupled with the whole surface of the floating gatexe2x80x9d is, therefore, a contradiction. Making sure that the second gate does not overlap the offset region implies that only part of the floating gate area contributes to the coupling ratio from control gate to floating gate and in turn explains why 14-15V is still typically used for programming the cell.
In a pending application, xe2x80x9cNon-volatile memory cellxe2x80x9d, PCT patent application Ser. No. PCT/BE98/00134, WO 9913513, filed Sep. 9, 1998, a device architecture is claimed which circumvents the above-mentioned problems yielding a very compact though still CMOS-compatible geometry that paves the way to high-density and low-voltage memory applications. Although the above-mentioned application Ser. No. PCT/BE98/00134, WO 99/13513 solves the above-mentioned problems, it still requires 3 polysilicon layers which is much more complicated for the processing of the chip than a double polysilicon scheme.
Other references to memory devices that are relevant with respect to the present invention are listed below: (1) U.S. Pat. No. 5,029,130, issued Jul. 2, 1991, listed inventor B. Yeh; (2) xe2x80x9cAn 18 Mb Serial Flash EEPROM for Solid-State Disk Applicationsxe2x80x9d, by D. J. Lee et al., paper presented at the 1994 Symposium on VLSI Circuits, tech. digest p.59; (3) xe2x80x9cA 5 Volt high density poly-poly erase Flash EPROM cellxe2x80x9d. by R. Kazerounian, paper presented at the 1988 Intemational Electron Devices Meeting, tech. digest p.436; (4) U.S. Pat. No. 5,572,054, issued on Nov. 5, 1996, listed inventors Wang et al. These references all suffer from a variety of problems such as a high processing complexity and/or the need for high erase voltages.
Yeh et al. show a split gate cell with a very complicated interpoly formation scheme which, again, makes this concept unsuited for embedded memory. The used erase voltage is still 15V although special processing features have been introduced specifically to enhance the interpoly conduction for efficient erasure. The papers by Lee and by Kazerounian show less details on processing issues, but it is clear from the disclosure that the erase voltages are in the order of 20V in order to tunnel through a polyoxide.
Wang et al. (U.S. Pat. No. 5,572,054) describes an electrically programmable and erasable memory device which comprises at least one transistor. This transistor comprises a substrate which is provided with a source, a drain and a channel region extending between the source and the drain. The substrate has a split point situated between the source and the drain which forms a separation between a first region extending from the split point towards the drain and a second region extending from the split point towards the source. A first insulating layer is applied on the substrate and extends in the second region over a portion of the source and the channel region. A second insulating layer is applied on the substrate in the first region, where it separates the substrate from a control gate. The second insulating layer further extends in the second region where it contacts the control gate. A floating gate is sandwiched between the first and second insulating layers and extends over a portion of the source to be capacitively coupled to the source. This transistor structure is commonly known in the art as a xe2x80x9csplit gatexe2x80x9d structure.
There are n-channel and p-channel devices with split gate transistors. In the n-channel devices, the source and drain are doped with an n-type dopant and the substrate is doped with a p-type dopant. In p-channel devices, the source and drain are doped with a p-type dopant and the substrate is doped with an n-type dopant. The device described in U.S. Pat. No. 5,572,054 is an n-channel device. This implies that electrons flow through the channel region from the drain towards the source. In p-channel devices, the electrons flow from source to drain, which implies in p-channel split gate transistors the floating gate is located in the region extending from the split point towards the drain.
The floating gate of the device described in U.S. Pat. No. 5,572,054 can be charged to obtain a programmed state and discharged to obtain a non-programmed or erased state of the memory cell. Programming the floating gate means that electrons are introduced onto the floating gate. Erasing means that electrons are removed from the floating gate. Assuming that the floating gate is in an erased state, i.e. positively charged, programming the transistor, i.e. charging the floating gate, is conducted as follows. A ground potential is applied to the drain, a low positive voltage (e.g. +1 V) is applied to the control gate and a high positive voltage (e.g. +12 V) is applied to the source. The high voltage difference between drain and source causes electrons to migrate through the channel from the drain towards the source, i.e. the channel region becomes conductive and is xe2x80x9cturned on.xe2x80x9d The positive voltage on the control gate serves to transfer the drain potential onto the split point. When the electrons reach the split point, they see a steep potential drop as the influence of the positive voltage on the control gate diminishes in this point. The steep potential drop is approximately equal to the source potential and causes them to be accelerated or xe2x80x9cheatedxe2x80x9d. Due to the capacitive coupling with the source, the floating gate attracts the heated electrons, which causes some of them to be injected through the first insulating layer onto the floating gate. This process continues until the positive charges on the floating gate are neutralised by the electrons injected onto it and the floating gate is no longer positively charged, which results in the portion of the channel region beneath the floating gate being xe2x80x9cturned offxe2x80x9d, i.e. it is no longer conductive. This method of charging the floating gate is commonly known in the art as channel hot electron injection (CHEI).
Assuming that the floating gate is in a programmed state, i.e. negatively charged, erasing the transistor, i.e. discharging the floating gate is conducted as follows. A ground potential is applied to the source and the drain, and a high positive voltage (e.g. +15 V) is applied to the control gate. The high potential of the control gate causes electrons on the floating gate to travel through the second insulating layer to the control gate by means of the Fowler-Nordheim tunneling mechanism, which is known to the person skilled in the art.
The memory cell described in U.S. Pat. No. 5,572,054 however has the disadvantage that high voltages are needed for both programming and erasing the memory cell. Because of these high voltages, the first and second insulating layers need to have a substantial thickness in order to avoid breakdown. Furthermore, particular circuits, such as for example charge pumping circuits, are required to achieve the high programming and erasing voltages, since these voltages are above the supply voltage of the device, which is commonly about 5 volts. This can lead to an increase in the size of the memory device.
An aim of the invention is to develop a high density memory device having fast programming capabilities, using low voltages, being scalable and being easy to process.
Another aim of the invention is to present an electrically programmable and erasable memory device in which the voltages used for programming and erasing are less than those used in the prior art.
The aim of the invention is achieved in that said first insulating layer and said overlap are dimensioned in such a way as to create a capacitive coupling between said floating gate and said drain enabling injection onto the floating gate of hot electrons generated by drain induced secondary impact ionisation.
The mechanism used in the device of the invention for programming the transistor, drain induced secondary impact ionisation, can be explained as follows. A voltage difference is applied over the channel region in such a way that hot electrons flow from source to drain. As these hot electrons impact on the drain, they transfer a certain amount of their energy onto the drain. As a result, the drain is ionised, meaning that electrons come loose from the drain. These so-called xe2x80x9csecondary electronsxe2x80x9d are heated as they receive energy from the electrons impacting on the drain. Due to the capacitive coupling of the floating gate with the drain, by which part of the voltage on the drain is induced on the floating gate, the secondary electrons are attracted by the floating gate. Some of them have sufficient energy to diffuse through the first insulating layer and be injected onto the floating gate. The mechanism of drain induced secondary impact ionisation allows the programming and erasing of the transistor at more moderate voltages with respect to the prior art.
In a preferred embodiment of the device of the invention, the substrate is negatively biased with respect to the source during programming of the transistor. Biasing the substrate negatively with respect to the source has the advantage that the electric field which is present over the first insulating layer and is caused by the voltage difference between the floating gate and the substrate, can be enhanced. An enhancement in this electric field causes the secondary electrons to be more attracted to the floating gate. As a result, biasing the substrate negatively with respect to the source can lead to an enhancement of the programming speed.
In a further preferred embodiment of the device of the invention, a drain junction is provided between the drain and the substrate, which drain junction has a depth larger than the overlap between the floating gate and the drain. This deep drain junction is preferably provided with a halo extension. By providing such a drain junction, the mechanism of drain induced secondary impact ionisation can be enhanced, resulting in a further enhancement of the programming speed.
The capacitive coupling between the floating gate and the drain is preferably constructed such that it enables tunnelling, preferably Fowler-Nordheim tunnelling, of electrons from said floating gate to said drain for erasing the transistor. In order to enable tunnelling of electrons from the floating gate and a target, a capacitive coupling between the floating gate and the target is required. This capacitive coupling is preferably between predetermined values. A capacitive coupling of too low value is undesirable for tunnelling, because this implies that there is either substantially no overlap between the floating gate and the target, or that the insulating layer between the floating gate and the target is too thick to enable tunnelling at a moderate voltage. A capacitive coupling of too high value is also undesirable for tunnelling, because a high capacitive coupling results in a large part of the voltage applied to the target being induced on the floating gate, so that at a moderate voltage, the voltage difference between the target and the floating gate remains too low to achieve tunnelling.
Programming the transistor of the device in one embodiment of the invention comprises the steps of applying a source voltage to the source, applying a control gate voltage to the control gate and applying a drain voltage to the drain. The drain voltage has a higher voltage value than the control gate voltage, which in its turn has a higher voltage value than the source voltage. As the control gate voltage is below the drain voltage, the device of the invention allows the use of more moderate voltages for programming with respect to the prior art.
Erasing the transistor of the device in one embodiment of the invention comprises the steps of applying a source voltage to the source, applying a control gate voltage to the control gate and applying a drain voltage to the drain. The drain voltage has a higher voltage value than the control gate voltage and the source voltage, which are preferably supplied with the ground potential. As a result of the suitable capacitive coupling between the floating gate and the drain as described above, the device of the invention allows the use of more moderate voltages for erasing with respect to the prior art.
Reading the transistor of the device of the invention comprises the steps of applying a source voltage to the source, applying a control gate voltage to the control gate and applying a drain voltage to the drain. The control gate voltage has a higher voltage value than the source voltage, which in its turn has a higher voltage value than the drain voltage. This method of reading the transistor can be termed xe2x80x9creverse read-out,xe2x80x9d because the third source voltage is higher than the drain voltage, which is preferably the ground potential. The reverse read-out has the advantage that a low voltage, preferably the ground potential, is applied to the drain during reading, which serves to avoid a leakage current from the floating gate to the drain.